The present invention relates to error performance analyzers. More specifically, the present invention relates to the method and apparatus for displaying eye diagrams of binary digit transmission using bit error ratio testers, or BERTs.
A fundamental measure of quality of digital circuits, switches, and transmission systems is the probability of any stored or transmitted bit being transmitted in error, or bit error ratio (BER). The BER is typically tested using a bit error ratio tester (BERT) which may include of a pattern generator and an error detector. The pattern generator and the error detector are often combined in a single unit though this is not required. They are, in fact, sometimes separate units. The pattern generator generates a known sequence of bits (sequence of zeros and ones) for transmission through a device under test (DUT). The error detector receives the bit sequence from the DUT representing the known bit sequence as transmitted through the DUT. The error detector compares the received bit sequence with the known bit sequence for error bit detection. An error bit is a bit that is sent to the DUT as a zero but transmitted by the DUT as a one, or a bit that is sent to the DUT as a one but transmitted by the DUT as a zero. Then, the number of error bits is compared with the number of bits sent. The ratio of the error bits to the sent bits is the bit error ratio, BER. With modern devices, the BER may be very low and may be on the order of 10xe2x88x9212 or even less.
As discussed, an error detector provides the BER as one measure of quality of the DUT. The BER is a single value ratio of the number of error bits compared to the total number of bits sent; however, the error detector does not show the quality of the signal (representing the bit sequence) received from the DUT. That is, the BER provided by the error detector does not show the quality of the signal behind the BER and provide no indications of the DUT performance regarding signal degradation, timing jitter, pulse degradation, intersymbol interference, or other quality issues. To obtain such information, the bit sequence from the DUT is typically displayed as an eye diagram using an oscilloscope. The eye diagram is a multivalued display overlapping all the 0-bit signals and 1-bit signals of the bit sequence. FIG. 3 illustrates a sample. eye diagram which is discussed in more detail herein below. The large open area in the center of the pulse is called the eye opening. The distance between the top and the bottom at the center of the pulse is called the eye height while the distance between the transitions is called the eye width. The uses of the eye diagram and the methods of generating the eye diagram using an oscilloscope are well known in the art.
In summary, for a comprehensive testing of a DUT, two devices are neededxe2x80x94an error detector and an oscilloscope. However, the use of the oscilloscope adds to the hardware requirements and costs to the DUT testing process. It would be preferable to display the eye diagram using the error detector alone. Accordingly, there is a need for a technique and an apparatus to obtain the BER as well as to display the eye diagram without the use of an oscilloscope.
These needs are met by the present invention. According to one embodiment of the present invention, a technique of displaying an eye diagram on an error performance analyzer is disclosed. First, a first bit sequence comprising 0-bits signified by a first bit voltage, VLB, and 1-bits signified by a second bit voltage, VHB, are received; the bits of the first bit sequence have a period. Then, beginning at a first delay time and repeating at each incremental time thereafter until at least one period is spanned, first combined voltage, VLC, and a second combined voltage, VHC, of the bits of the first bit sequence are determined by comparing the first bit sequence of bits to a second bit sequence, the bit second sequence being substantially similar to the first bit sequence. Finally, the first combined voltages and second combined voltages are displayed as an eye diagram.
According to another aspect of the invention, an eye diagram is displayed using a first and a second combined voltages. First, a first bit sequence comprising 0-bits signified by a first bit voltage, VLB, and 1-bits signified by a second bit voltage, VHB, are received; the bits of the first bit sequence having a period. Then, beginning at a first delay time and repeating at each incremental time thereafter until at least one period is spanned, first combined voltage spread and a second combined voltage spread of the bits of the first sequence are determined by comparing the first bit sequence to a second bit sequence, the second bit sequence substantially similar to the first bit sequence. Finally, the first combined voltage spreads and second combined voltage spreads are displayed as an eye diagram.
According to yet another aspect of the invention, an apparatus includes a processor and storage connected to the processor, the storage including instructions for the processor to receive a first bit sequence comprising 0-bits signified by a first bit voltage, VLB, and 1-bits signified by a second bit voltage, VHB, the bits of the first bit sequence having a period. Further, additional instructions include the instructions to determine, beginning at a first delay time and repeating at each incremental time thereafter until at least one period is spanned, first combined voltage spread and a second combined voltage spread of the bits of the first sequence by comparing the first bit sequence to a second bit sequence, the second bit sequence substantially similar to the first bit sequence, and instructions to display the first combined voltage spreads and second combined spreads.